1. Field of the Invention
The present invention relates to a VLSI system, and more particularly to a self-timed latch circuit for a high-speed VLSI system.
2. Description of the Conventional Art
Generally, latches and flip-flops which are used as data storing devices are the most basic elements for a VLSI system. Particularly, the storing devices are mostly synchronized by clock signals. In that case, transition of the clock signal should be simultaneously occurred in all synchronizing points of of a system wherein the data storing devices (the latches and flipflops) are located. However, since in real situations the clock signal passes through a plurality of different wiring paths respectively having different loads, the clock signal arrives at each point by having a different time delay.
As a result, the change of the time delay generated while the clock signal is being dispersed results in skew of the clock signal which leads to serious problems such as, for example, false output latching. Further, in order to uniformly disperse the clock signal without any skew, increase of the design costs must be attended. Accordingly, generally a self-timed latch circuit is used for solving such problems. Since the self-timed latch circuit does not apply the clock signal, the clock skew problem and the clock dispersion costs can be reduced.
FIGS. 1A and 1B illustrate self-timed latch circuits in a SR type which are used in a synchronizing system. As shown in FIG. 1A, an active-low SR latch of a NAND type consists of NAND gates which receives external signals S, R, respectively, the NAND gates being connected to each other in a back-to-back mode. While, as shown in FIG. 1B, an active-high SR latch of a NOR type consists of NOR gates which receives external signals S, R, respectively, also the NOR gates being connected to each other in the back-to-back type. Such self-timed latch circuits have a feedback-type connecting configuration in which an output signal Q or Qb is used as an input signal of the logic gate NAND or NOR, and can be used for driving large load by which each output terminal thereof is connected with a driver inverter. Here, the external signals R, S are reset and set signals, respectively.
In the conventional self-timed latch circuit, when the external signals S, R are respectively at a high level, as shown in FIG. 1A, signal Q, Qb outputted from the NAND-type SR latch maintain previous values Q.sub.-- 1, Qb.sub.-- 1, respectively. When one of the external signals S, R is transited to a low level in such condition, a corresponding output signal becomes a high level and thereby a logic state is accordingly changed. Various changes of the output signals Q, Qb with respect to the external signals S, R are illustrated as a truth table in Table 1.
TABLE 1 ______________________________________ SET RESET Q Qb ______________________________________ 1 1 Q.sub.-- 1 Qb.sub.-- 1 0 1 1 0 1 0 0 1 0 0* 1 1 ______________________________________ *not allowed
While, as shown in FIG. 1B, when the external signals S, R are respectively at a low level, signals Q, Qb outputted from the NOR-type SR latch maintain previous values 0.sub.-- 1, Qb.sub.-- 1, respectively. When one of the external signals S, R is transited to a high level in such condition, a logic state of a corresponding output signal is accordingly changed. In table 2, various changes of the output signals Q, Qb with respect to the external signals S, R are illustrated as a truth table in following Table 2.
TABLE 2 ______________________________________ SET RESET Q Qb ______________________________________ 0 0 Q.sub.-- 1 Qb.sub.-- 1 1 1 1 0 1 0 0 1 1* 1* 0 0 ______________________________________ *not allowed
However, the conventional self-timed latch circuit has several problems due to the back-to-back connection. More specifically, a critical path formed by the feedback connection considerably decreases a processing speed of the latch circuit. Such decrease of the processing speed thereof becomes more serious as load of a output terminal becomes large, because the output terminal having the large load exists on the critical path.
In addition, since the conventional self-timed latch circuit has a serial output system by the feedback connection, there must be time difference between the output signals Q, Qb. Therefore, the output signals Q, Qb are generated asymmetrically, and thus it is impossible to supply stable signals to a circuit which requires both of the output signals Q, Qb.
Further, the conventional self-timed latch circuit of the NAND or NOR type has a serial connection of an NMOS or PMOS transistor. Therefore, the serial connection configuration unavoidably increases the size of the transistor and decreases the processing speed. Particularly, those problems are more seriously induced in the NOR-type SR latch having the serial connection of the PMOS transistor, and also there is large difference in performance between the conventional active-low and active-high self-timed latch circuits.